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1 ? fn4725.4 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 1999, 2000, 2004. all rights reserved all other trademarks mentioned are the property of their respective owners. hip1011d, HIP1011E dual slot pci hot plug controllers the hip1011d, HIP1011E are the first ics available for independent control of two pci hot-plug slots. the hip1011d has all the features and function ality of two single pci hot-plug slot controllers such as the hip1011a but in the same foot print area. like the single slot hip1011b, the HIP1011E does not monitor output voltage nor respond to undervoltage conditions. the hip1011d, HIP1011E are designed to be physically placed in close proximity to two adjacent pci slots thus reducing layout complexity and placement costs in assembly. the hip1011d, HIP1011E provides independent power control to each slot and the addition of discrete power mosfets and a few passive components creates two complete power control soluti ons. the ic integrates the +12v and -12v current sensin g switches for each slot. overcurrent (oc) protection is provided by sensing the voltage across external current- sense resistors. in addition, on-chip references are used to monitor the +5v, +3.3v and +12v outputs for undervoltage (uv) conditions *. the two pwron inputs control the stat e of the switches, one each for slot a and slot b outputs. during an oc condition on any output, or a uv condition on th e +5v, +3.3v or +12v outputs *, a low (0v) is asserted on the associated fltn output and all associated switches are latched-off. the outputs servicing the adjacent slot are unaffected. the time to fltn signal going low and mosfet latch off is user determined by a single capacitor from each fltn pin to ground. this added feature enables the hip1011d, HIP1011E to ignore system noise transients. the fltn latch is cleared when the pwron in put is toggled low again. during initial power-up of the main vcc supply (+12v), the pwron input is inhibited from turning on the switches, and the latch is held in the reset state until the vcc input is greater than 10v. user programmability of the overcurrent threshold and turn- on slew rate is provided. a resistor connected to the ocset pin programs the overcurrent threshold for both slots. capacitors connected to the ga te pins set the turn-on rate. * uv references do not apply to HIP1011E. features ? independent power control of 2 pci slots ? turn-off delay time adjustability ? internal mosfet switches for +12v and -12v outputs ? p interface for on/off control and fault reporting ? adjustable overcurrent protection for all eight supplies ? provides fault isolation ? adjustable turn-on slew rate ? minimum parts count solution ? no charge pump ? 100ns response time to overcurrent ? pb-free package options ? tape & reel packing with ?-t? part number suffix applications ? pci hot-plug pinout hip1011d, HIP1011E (ssop) top view ordering information part number temp. range (c) package pkg. dwg. # hip1011dca 0 to 70 28 ld ssop m28.15 hip1011dcaza (note) 0 to 70 28 ld ssop (pb-free) m28.15 HIP1011Eca 0 to 70 28 ld ssop m28.15 note: intersil pb-free products em ploy special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow te mperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020b. 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 m12vo_1 m12vg_1 12vin_1 m12vo_2 m12vg_2 12vg_2 12vo_2 m12vin_2 12vo_1 12vin_2 12vg_1 m12vin_1 3visen_2 3vs_2 3v5vg_2 pwron_2 5visen_2 fltn_2 vss ocset pwron_1 fltn_1 5vs_1 5visen_1 3visen_1 3vs_1 3v5vg_1 5vs_2 data sheet june 2004
2 typical application m12vo_2 m12g_2 pwron_1 m12vin_1 12vo_2 12vin_1 12vg_2 3visen_1 3vs_1 3v5vg_1 ocset 3visen_2 3vs_2 3v5vg_2 12vin_2 m12vin_2 fltn_1 vss pwron_2 fltn_2 5vs_2 5visen_2 m12vo_1 m12g_1 12vg_1 12vo_1 5vs_1 5visen_1 hip1011d, HIP1011E 5v bus 3.3v bus -12v bus +12v bus c1 c2 c3 c4 r1 r2 r3 r4 q1 q2 q3 q4 r5 to system controller slot 2 from 5v 3.3v 12v -12v c5 c6 opt. opt. system controller slot 1 -12v 12v 3.3v 5v figure 1. hip1011d, HIP1011E
3 simplified schematic (1 /2 hip1011d, HIP1011E) fltn 5v s 3v5v g 5v isen 3v s ocset 3v isen 12v in 12v g 12v o m12v in m12v g m12v o pwron gnd 12v in power-on reset 12v in m12v in 12v in 12v in 100a 0.3 ? 0.7 ? fault latch v ocset 5v zener reference 12v in 5v ref 5v ref 4.6v inhibit 12v in set (low = fault) reset 12v in low = fault low when 12v in < 10v high = switches on high = fault + - comp - + comp - + + - comp + 2.9v inhibit comp + - 10.6v inhibit comp + - comp - + + - 12v in 12v in comp - + + - - figure 2. tied high in hip1011d tied low in HIP1011E hip1011d, HIP1011E
4 pin descriptions pin no. designator function description 15, 28 m12vin -12v input -12v supply input. also prov ides power to the -12v overcurrent circuitry. 4, 11 fltn fault output 5v cmos fault output; low = faul t. an optional capacitor may be placed from this pin to ground to provide additional immuni ty from power supply glitches. 20, 23 3v5vg 3.3v/5v gate output drive the gates of the 3.3v and 5v mosfets. connect a capacitor to ground to set the startup ramp. during turn on, this capacitor is charged with a 25 a current source. hip1011d uv comparator disabled w hen this pin is below 9.6v nominal. 21, 22 12vin 12v input 12v supply input for ic and 12vo. bo th 12vins to be connected to a single +12v supply. 16, 27 3visen 3.3v current sense connect to the load side of the current sense resistor in series wi th source of external 3.3v mosfet. 17, 26 3vs 3.3v source connect to source of 3.3v mosf et. this connection along with (3visen) senses the voltage drop across the sense resistor. 19, 24 5vs 5v source connect to source of 5v mosfet sw itch. this connection along with (5visen) senses the voltage drop across the sense resistor. 18, 25 5visen 5v current sense connect to the load side of the curr ent sense resistor in series with source of external 5v mosfet. 3, 12 pwron power on control controls all four switches . high to turn switches on, low to turn them off. 6, 9 12vg gate of internal pmos connect a capacitor between 12v g and 12vo to set the startup ramp for the +12v supply. this capacitor is charged with a 25 a current source during startup. hip1011d uv comparator disabled when this pin >1.4v nominal. 7, 8 12vo switched 12v output switched 12v output. rated for 0.5a. 2, 13 m12vg gate of internal nmos connect a capacitor between m12vg and m12vo to set the startup ramp for the m12v supply. this capacitor is charged with 25 a during startup. 1, 14 m12vo switched -12v output switched -12v output. rated for 0.1a. 10 ocset overcurrent set connect a resistor from this pin to ground to set the overcurrent trip point of all eight switches. all eight overcurrent trips can be programmed by changing the value of this resistor. the default (6.04k ? , 1%) is compatible with the maximum allowable currents as outlined in the pci specification. 5 vss ground connect to common of power supplies. hip1011d, HIP1011E
5 absolute maximum rati ngs thermal information 12vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +14.0v 12vo, 12vg, 3v5vg . . . . . . . . . . . . . . . . . . . . -0.5v to 12vin+0.5v m12vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -14.0v to +0.5v m12vo, m12vg. . . . . . . . . . . . . . . . . . . . . . v m12vin -0.5v to +0.5v 3visen, 5visen . . . . . . . . . . -0.5v to the lesser of 12vin or +7.0v voltage, any other pin. . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +7.0v 12vo output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3a m12vo output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8a esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kev (hbm) operating conditions 12vin supply voltage range . . . . . . . . . . . . . . . . +10.8v to +13.2v 5v and 3.3v input supply tolerances . . . . . . . . . . . . . . . . . . . . . . 10% 12vo output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to +0.5a m12vo output current . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to +0.1a temperature range (t a ) . . . . . . . . . . . . . . . . . . . . . . . . 0c to 70c thermal resistance (typical, note 1) ja (c/w) ssop package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . 150c maximum storage temperature range . . . . . . . . . . . -65c to 150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300c (ssop - lead tips only) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. 2. all voltages are relative to gnd, unless otherwise specified. electrical specifications nominal 5.0v and 3.3v input supply voltages, 12v in = 12v, m12v in = -12v, t a = t j = 0 to 70c, unless otherwise specified parameter symbol test conditions min typ max units 5v/3.3v supply control 5v overcurrent threshold i oc5v see figure 24, typical application - 8 - a 5v overcurrent threshold voltage v oc5v_1 v ocset = 0.6v 33 42 50 mv 5v overcurrent threshold voltage v oc5v_2 v ocset = 1.2v 70 80 90 mv 5v undervoltage trip threshold v 5vuv (hip1011d only) 4.42 4.65 4.8 v 5v undervoltage fault response time t 5vuv (hip1011d only) - 110 160 ns 5v turn-on time (pwron high to 5vout = 4.75v) t on5v c 3v5vg = 0.022 f, c 5vout = 2000 f, r l = 1 ? -6.5-ms 3v overcurrent threshold i oc3v see figure 24, typical application - 10 - a 3v overcurrent threshold voltage v oc3v_1 v ocset = 0.6v 41 52 62 mv 3v overcurrent threshold voltage v oc3v_2 v ocset = 1.2v 89 98 108 mv 3v undervoltage trip threshold v 3vuv (hip1011d only) 2.74 2.86 2.98 v 3v undervoltage fault response time t 3vuv (hip1011d only) - 110 160 ns 3v5vg undervoltage enable threshold voltage v 3v5vgenvth (hip1011d only) - 9.6 - v 3v turn-on time (pwron high to 3v out = 3.00v) t on3v c 3v5vg = 0.022 f, c 3vout = 2000 f, r l =0.43 ? -6.5-ms 3v5vg v out high vout_hi_35vg pwron = high, fltn = high 11.5 11.8 - v gate output charge current ic 3v5vg pwron = high, v 3v+5vg = 4v 19 25.0 29 a gate turn-on time (pwron high to 3v5vg = 11v) t on3v5v c 3v5vg = 0.033 f, 3v5vg rising 10% to 90% - 280 - s gate turn-off time t off3v5v c 3v5vg = 0.033 f, 3v5vg falling 90% to 10% - 2 - s hip1011d, HIP1011E
6 +12v supply control on resistance of internal pmos r ds(on)12 pwron = high, i d = 0.5a t a = t j = 25c - 0.3 0.35 ? t a = t j = 70c - 0.35 0.50 ? overcurrent threshold i oc12v_1 v ocset = 0.6v 0.5 0.6 0.9 a overcurrent threshold i oc12v_2 v ocset = 1.2v 1.2 1.4 1.8 a 12v undervoltage trip threshold v 12vuv (hip1011d only) 10.25 10.6 10.8 v undervoltage fault response time t 12vuv (hip1011d only) - 110 - ns gate charge current ic 12vg pwron = high, v 12vg = 10v 1925.029 a turn-on time (pwron high to 12vg = 1v) t on12v c 12vg = 0.033 f, 12vg falling 90% - 10% - 16 - ms turn-off time t off12v c 12vg = 0.022 f, 12vg rising 10% - 90% - 3 - s -12v supply control on resistance of internal nmos r ds(on)m12 pwron = high, i d = 0.1a t a = t j = 25c - 0.7 1 ? t a = t j = 70c - 1.0 1.3 ? overcurrent threshold i oc12v_1 v ocset = 0.6v 0.13 0.17 0.25 a overcurrent threshold i oc12v_2 v ocset = 1.2v 0.23 0.36 0.52 a gate output charge current ic m12vg pwron = high, v 3vg = -10v 19 25 29 a turn-on time (pwron high to m12vo = -10.8v) t onm12v c m12vg = 0.033 f, c m12vo = 50 f, r l = 120 ? -16-ms turn-off time t offm12v c m12vg = 0.033 f, m12vg falling 90% to 10% - 3 - s m12vin input bias current ib m12vin pwron = high - 2.5 5 ma control i/o pins supply current i vcc -5.38ma ocset current i ocset 93 100 107 a overcurrent fault response time t oc - 500 960 ns pwron threshold voltage v thpwron 1.0 1.6 2.1 v fltn output low voltage v fltn,ol i fltn = 0.9ma - 0.25 0.4 v fltn output high voltage v fltn,oh i fltn = 0 to -4ma 3.5 4.3 - v fltn output latch threshold v fltn, th fltn high to low transition 1.8 2.3 3 v 12v power on enable threshold v por, thrise v cc voltage rising 9.4 10 10.2 v 12v power on reset threshold v por, thfall v cc voltage falling 8.9 9.3 9.6 v electrical specifications nominal 5.0v and 3.3v input supply voltages, 12v in = 12v, m12v in = -12v, t a = t j = 0 to 70c, unless otherwise specified (continued) parameter symbol test conditions min typ max units hip1011d, HIP1011E
7 introduction the hip1011d and HIP1011E are the first dual pci slot ic devices designed to provide control and protection of the four pci power supplies independently to two pci slots. like the widely used hip1011 this device complies with the pci hot plug specification facilitatin g the service, upgrading or expansion of pci based servers without the need to power down the server. the hip1011d protects against overcurrent (oc) for the -12v, +12v, +3.3v, +5v and undervoltage (uv) conditions for the +12v, +3.3v, +5v supplies. the HIP1011E only responds to oc conditions. figure 1 illustrates the typi cal implementation of the hip1011d, HIP1011E. additional components for optimizing performance for particular applic ations, or desired features may be necessary. key feature description and operation the hip1011d/e, four power mosfets and a few passive components as configured in figure 1, create a small yet complete power control solution for two pci slots. it provides an oc trip level greater than the maximum pci specified current for each supply to each slot. oc monitoring and protection for the 3.3v and 5v supplies is provided by sensing the voltage across external current-sense resi stors. for the +12v and -12v inputs, oc protection is provided internally. on-chip references in the hip1011d are used to monitor the +5v, +3.3v and +12v outputs for uv conditions. during an oc condition on any output, or a uv condition on the +5v, +3.3v or +12v outputs (hip1011d only), all slot spec ific mosfets are immediately latched-off and a low (0v) is presented to the appropriate fltn output. during initial power-up of the main v cc supply (+12v), the pwron inputs are inhibited from turning on the switches, and the latch is held in the reset state until the v cc input is greater than 10v. after a fault has been asserted and fltn is latched low cycling pwron low then high will clear the fltn latch. user programming of the oc thresholds for both controlled slots is provided by a single resistor connected to the ocset pin along with r sense . in addition delay time to latch off after a fault condition can be increased by increasing the fltn to ground capacitance and the turn-on ramp rate can be increased by increasing the gate pin capacitance. customizing circuit performance overcurrent (oc) set functionality and resistor choice the hip1011d/e allows easy custom programming of the oc levels of all 4 supplies simultaneously for both pci slots by simply changing the resistor value between ocset, (pin 10), and ground. the r ocset value and the ocset 100 a current source sets a voltage that is used in each of eight comparators, (one for each supply for both slots). the voltages developed across the 3.3v and 5v sense resistors are applied to the inputs of their respective comparators. the +12v and -12v currents are sensed internally with pilot devices. once any comparator trips, that output is fed through logic circuits resulting in the appropriate fltn, (pin 4 or pin 11), going low, indicating a fault condition on that particular slot. because of the internal current monitoring of the +12v and -12v switches, th eir programming flexibility is limited to r ocset changes. the 3.3v and 5v overcurrent trip points depend on both r ocset and the value chosen for each sense resistor. see table 1 to determine oc protection levels relative to choice of r ocset and r sense values. overcurrent design guidelines and recommendations are as follows: 1. for pci applications, set r ocset to 6.04k ? , and use 5m ? 1% sense resistors (see figure 24). 2. for non pci specified applications, the following precautions and limitations apply: a. do not exceed the maximum power of the integrated nmos and pmos. high power dissipation must be coupled with effective thermal management. the integrated pmos has an r ds(on) of 0.3 ? . thus, with 1a of steady load current on each of the pmos devices the power dissipation is 0.6w. the thermal impedance of the package is 95 degrees celsius per watt, limiting the average dc current on the 12v supply to about 1a on each slot and imposing an upper limit on the r ocset resistor. do not use an r ocset resistor greater than 15k ? . the average current on the -12v supply should not exceed 0.7a. since the thermal restrictions on the +12v supply are more severe, the +12v supply restricts the use of the hip1011 to applications where the 12v supplies draw relatively little current. since both supplies only have one degree of freedom, the value of r ocset , the flexibility of programming is quite limited. for applications where more power is required on the +12v supply, contact your local intersil sales representative for information on other hot plug solutions. b. do not try to sense voltages across the external sense resistors that are less than 33m v. spurious faults due to noise and comparator input sensitivity may result. the minimum recommended r ocset value is 6k ? . this will set the nominal oc voltage thresholds at 52mv and 42mv for the 3.3v and 5v comparators respectively. this is the voltage level at which the oc fault (i out x r sense ) will occur. c. minimize v rsense so as to not sign ificantly reduce the voltage delivered to the adapter card. remember pcb trace and connector distribution voltage losses also need to be considered. make sure that the r sense resistor can adequately handle the dissipated power. for best results use a 1% precision resistor with a low temperature coefficient. d. minimize external fet r ds(on) . low r ds(on) or multiple mosfets in parallel are reco mmended. see intersil for a complete selection of mosfet offerings. hip1011d, HIP1011E
8 time delay to latch-off time delay to latch-off allows for a predetermined delay from an oc or uv in the hip1011d or an oc in the HIP1011E event to the simultaneous latch- off of all four supply switches of the affected slot. this delay period is set by the capacitance value to ground from the fltn pins for each slot. this capacitance value tailors the fltn signal going low ramp rate. this provides a delay to the fault signal latch-off threshold voltage, fltn, vth. by increasing this time, the hip1011d/e delays immediate latch-off of the bus supply switches, thus ignoring transient faults. see additional information in the ?using the hip1011dev al1 platform? section of this data sheet. the HIP1011E has all features of the hip1011d but it does not respond to uv events. caution: the primary purpose of a protection device such as the hip1011d/e is to quickly isolate a faulted card from the voltage bus. delaying the time to latch-off works against this primary concern so care must be taken when using this feature. ensure adequate sizing of external fets to carry additional current during time out period. understand that voltage bus disruptions must be minimized for the time delay period in the event of a crow bar failure. devices using an unadjustable preset delay to latch-off time present the user with the in ability to eliminate these concerns increasing cost and the chance of additional ripple through failures. hip1011d, HIP1011E soft start and turn-off considerations the hip1011d/e does allow the us er to select the rate of ramp up on the voltage supplies. this startup ramp minimizes in-rush current at startup while the on card bulk capacitors charge. the ramp is created by placing capacitors on m12vg to m12vo, 12vg to 12vo and 3v5vg to ground. these capacitors are each charged up by a nominal 25 a current during turn on. the same value for all gate timing capacitors is recommended. a recommended minimum value of 0.033 f as a smaller value may cause overcurrent faults at power up. this recommendation results in a nominal gate voltage ramp rate of 0.76v/ms. the gate capacitors must be discharged when a fault is detected to turn off the power fets. thus, larger caps slow the response time. if the gate capacitors are too large the hip1011d/e may not be able to adequately protect the bus or the power fets. the hip1011d/e have internal discharge fets to discharge the load when disabled. upon turn-off these internal switches on each output discharge the load capacitance pulling the output to gnd. these switches are also on when pwron is low thus an open slot is held at the gnd level. decoupling precautions and recommendations for the hip1011d/e proper decoupling is a particular concern during the normal switching operation and especially during a card crowbar failure. if a card experiences a crow bar short to ground, the supply to the other card will experience transi ents until the faulted card is isolated from the bus. in addition the common ic nodes between the two sides can fluctuate unpredictably resulting in a false latch-off of the second slot. additionally to the mother board bulk capacitance, it is recommended that 10 f capacitors be placed on both the +12v and -12v lines of the hip1011d/e as close to the chip as possible. recommended pcb layout design best practices to ensure accurate current sensing, pcb traces that connect each of the current sense resistors to the hip1011d/e must not carry any load current. this can be accomplished by two dedicated pcb kelvin traces directly from the sense resistors to the hip1011d/e (see examples of correct and incorrect layouts below in figure 3). to reduce parasitic inductance and resist ance effects, maximize the width of the high-current pcb traces. table 1. supply how to determine +25c nominal ( 10%) i oc for each supply +3.3v i oc ((100 a x r ocset )/11.5)/r rsense +5.0v i oc ((100 a x r ocset )/14.5)/r rsense +12v i oc (100 a x r ocset )/1 -12v i oc (100 a x r ocset )/3.4 correct to hip1011d/e vs and visen to hip1011d vs and visen current sense resistor incorrect figure 3. sense resistor pcb layout hip1011d, HIP1011E
9 typical performance curves figure 4. r on vs temperature figure 5. uv trip vs temperature (hip1011d only) figure 6. 12 uv trip vs temperature (hip101 1d only) figure 7. oc vth vs temperature figure 8. bias current vs temperature figure 9. 12v enable and reset threshold voltages vs temperature 340 320 300 280 260 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 1000 900 800 700 600 pmos r on +12 (m ? ) nmos r on -12 (m ? ) temperature (c) nmos -12 r on pmos +12 r on 4.632 4.631 4.630 4.629 4.626 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 5v uvtrip (v) 3.3v uvtrip (v) temperature (c) 5 uv 4.628 4.627 2.862 2.861 2.860 2.859 2.858 3.3 uv 10.59 10.57 10.55 10.53 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 12 uv trip (v) temperature (c) 100 85 70 55 40 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 oc vth (mv) temperature (c) 3v ocvth, vocset = 1.2v 5v ocvth, vocset = 1.2v 3v ocvth, vocset = 0.6v 5v ocvth, vocset = 0.6v 6 5 4 3 2 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 abs 12v bias (ma) temperature (c) +12v bias -12v bias 10.0 9.75 9.5 9.25 9.0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 +12v thresholds (v) temperature (c) +12v power on enable +12v power on reset hip1011d, HIP1011E
10 figure 10. +12v overcurrent level vs temperat ure figure 11. -12v overcurrent vs temperature figure 12. ocset current vs temperature figure 13. fltn latch-off threshold voltage vs temperature figure 14. overcurrent and undervoltage to fltn response time vs temperature typical performance curves (continued) 1.5 1.25 1.0 0.75 0.5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 temperature (c) vocset = 1.2v vocset = 0.6v +12v overcurrent (a) 0.4 0.3 0.2 0.1 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 temperature (c) -12v overcurrent (a) vocset = 1.2v vocset = 0.6v 102 101 100 99 98 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 ioc set (a) temperature (c) 2.4 2.35 2.3 2.25 2.2 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 temperature (c) fltn latch off threshold (v) ov/uv to fault response time (ns) 100 90 80 70 60 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 temperature (c) hip1011d, HIP1011E
11 using the hip1011deval1 platform general and biasing information the hip1011deval1 platform (figure 24) comes as a three part set consisting of 1 motherboard emulator and 2 load cards. this evaluation platform allows a designer to evaluate and modify the performance and functionality of the hip1011d or HIP1011E in a simple environment. test point numbers (tp#) correspond to the hip1011d/e device (u5) pin numbers. thus tp3 and tp12 are pwron_2 and pwron_1 respectively. these 2 pins are the hip1011d/e control inputs for each of the 2 integrated but independent pci power cont rollers in the hip1011d/e. on the hip1011deval1 platform are 4 huf76132sk8, (11.5m ? , 30v, 11.5a) n-channel power mosfets, (q1- q4) these are used as the extern al switches for the +5v and +3.3v supplies to the load card connectors, p1 and p2. current sensing is fac ilitated by the four 5m ? 1w metal strip resistors (r1-r4), the voltages developed across the sense resistors are compared to references on board the hip1011d/e. the hip1011deval1 platform is powered through the j1 to j5 connector jacks near the top of the board (see table 2 for bias voltage assignments.) after properly biasing the hip1011d/e and ensuring there is an adequate ground return from the hip1011deval1 platform to the power supplies, (otherwise anomalous and unpredictable results will occur) signal the pwron inputs low then insert the load cards as shown in figure 15. signaling either or both pwron pins high (>2.4v) will turn on the appropriate fet switches and apply voltage to the load cards. * the hip1011deval board is supplied with a hip1011d installed and in addition a loose packed HIP1011E. evaluating time de lay to latch-off provided for delay to latch-off evaluation are 2 locations for smd capacitors, c7 and c8. filling these locations places a capacitor to ground from each of the hip1011d/e fltn pins thus tailoring the fltn signal going low ramp rate. this provides a delay to the fault signal latch-off threshold voltage, fltn vth. by increasing this time the hip1011d delays immediate latch-off of the bus supply switches, thus ignoring transient oc and uv conditions. see table 3 illustrating the time it takes for switch gate turn-off from the fltn start of response to an oc or uv condition. the fltn response to an oc or uv condition is 110ns. see figures 20 through 23 for waveforms. the intent of any protection dev ice is to isolate the supply quickly so a faulty card does not drag down a supply. a longer latch-off delay results in less isolation from a faulty card to supply. table 2. hip1011deval1 bias assignments j1 j2 j3 j4 j5 gnd +5v -12v +12v +3.3v load cards hip1011d figure 15. correct installation of load cards table 3. c7 and c8 value open 0.001 f0.01 f0.1 f fltn to gate response 0.1 s0.44 s2.9 s28 s 3v5vg fltn fltn, vth figure 16. timing diagram 1ns 10ns 100ns 1s 10s 100s 1ms 10ms 0.001f 0.1f 1f 10f open 0.01f figure 17. typical oc/uv to vg response vs fltn cap hip1011d, HIP1011E
12 typical performance curves (continued) figure 18. hip1011deval1 3.3v supply current as each slot controller turns on into load card figure 19. hip1011deval1 3.3v supply current as controller 1 turns on into shorted load card figure 20. fltn to 35vg delay figure 21. fltn to 35vg delay figure 22. fltn to 35vg delay figure 23. fltn to 35vg delay ch1 and ch2 voltage (5v/div) time (100ms/div) ch3 current (2a/div) supply current enable 2 enable 1 ch2 ch1 ch3 ch1 and ch2 voltage (5v/div) time (100ms/div) ch3 current (2a/div) ch2 enable 2 enable 1 supply current ch1 voltage (2v/div) time (1s/div) fltn = open vg fltn voltage (2v/div) time (1s/div) fltn = 0.001f vg fltn voltage (2v/div) time (2 s/div) fltn = 0.01 f fltn vg voltage (2v/div) time (10s/div) fltn = 0.1f vg fltn hip1011d, HIP1011E
13 table 4. hip1011deval1 board component listing component designator component name component description u1 hip1011dcb or HIP1011Ecb dual pci hotplug controller intersil, hip1011dcb or HIP1011Ecb dual pci hotplug controller q1, q2, q3, q4 huf76132sk8 (or equivalent) huf76132sk8 (or equivalent), 11.5m ? , 30v, 11.5a logic level n-channel mosfet r1 - r4 sense resistor for 3.3v and 5v supplies dale, wsl-2512 5m ? metal strip resistor c1 - c6 gate timing capacitors 0.033 f 805 chip capacitor r5 overcurrent set resistor 6k ? 805 chip resistor c7, c8 (not provided) latch-off delay capacitors place provided for 805 chip cap r6, r7 led series resistors 470 ? 805 chip resistors d1, d2 fault indicating led green smd led tp1 - tp28 test point for corresponding device pin number p1, p2 connectors for load cards sullins ezm06drxh figure 24. m12vo_2 m12g_2 pwron_1 m12vin_1 12vo_2 12vin_1 12vg_2 3visen_1 3vs_1 3v5vg_1 ocset 3visen_2 3vs_2 3v5vg_2 12vin_2 m12vin_2 fltn_1 vss pwron_2 fltn_2 5vs_2 5visen_2 m12vo_1 m12g_1 12vg_1 12vo_1 5vs_1 5visen_1 hip1011d, HIP1011E 5v bus -12v bus +12v bus c1 c2 c3 c4 r1 r2 r3 r4 q1 q2 q3 q4 r5 tp3 tp12 p1 j1 j3 j4 j5 3.3v bus j2 r6 d1 tp11 tp4 r7 d2 p2 c5 c6 c7 c8 no pop no pop u1 12v -12v 5v 3.3v 5v 3.3v -12v 12v hip1011d, HIP1011E
14 rl1 3.3v load board resistor 1.1 ? , 10w rl2 5.0v load board resistor 2.5 ? , 10w rl3 +12v load board resistor 47 ? , 5w rl4 -12v load board resistor 240 ? , 2w cl1, cl2 +3.3v and +5.0v load board capacitors 2200 f cl3, cl4 +12v and -12v load board capacitors 100 f table 4. hip1011deval1 board component listing (continued) component designator component name component description figure 25. load board (2x) rl1 cl1 3.3v rl2 cl2 5.0v rl3 cl3 +12v rl4 cl4 -12v hip1011d, HIP1011E
15 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com hip1011d, HIP1011E shrink small outline plastic packages (ssop) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mo ld flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include inte rlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual in- dex feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dam bar protrusion. allowable dam- bar protrusion shall be 0.10mm (0.004 inch) total in excess of ?b? dimension at maximum material condition. 10. controlling dimension: inches. c onverted millimeter dimensions are not necessarily exact. index area e d n 123 -b- 0.17(0.007) c a m bs e -a- b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 m28.15 28 lead shrink narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.053 0.069 1.35 1.75 - a1 0.004 0.010 0.10 0.25 - a2 - 0.061 -1.54- b 0.008 0.012 0.20 0.30 9 c 0.007 0.010 0.18 0.25 - d 0.386 0.394 9.81 10.00 3 e 0.150 0.157 3.81 3.98 4 e 0.025 bsc 0.635 bsc - h 0.228 0.244 5.80 6.19 - h 0.0099 0.0196 0.26 0.49 5 l 0.016 0.050 0.41 1.27 6 n28 287 0 o 8 o 0 o 8 o - rev. 0 2/95

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